Semiconductor integrated circuit (IC) fabrication involves forming multiple material layers with designed patterns on a semiconductor wafer. Each layer has to be aligned with previous layers such that the formed circuit can function properly. Various marks are used for this purpose. For example, alignment marks are used for alignment between a photomask and the semiconductor wafer. In another example, overlay marks are used to monitor overlay deviation between the layers on the wafer. As semiconductor technology continues progressing to circuit layouts having smaller feature sizes, the alignment requirement becomes more stringent and the alignment/overlay marks are expected to take less wafer area. However, the current overlay marks take a large chip area and cannot be shrunk much due to the resolution of the optical tool used to monitor the overlay marks. In this situation, more chip areas are needed for the overlay marks, resulting in higher manufacturing cost and chip cost. Furthermore, if additional overlay marks are needed in the circuit areas, it is more challenging due to overlay mark size and the place/route concern. It is desired, therefore, to provide an overlay measurement method and a structure for monitoring and controlling in-chip overlay with less silicon area.